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| 1/39 may 2000 m28w160bt m28w160bb 16 mbit (1mb x16, boot block) low voltage flash memory n supply voltage Cv dd = 2.7v to 3.6v: for program, erase and read Cv ddq = 1.65v or 2.7v: input/output option Cv pp = 12v: optional supply voltage for fast program n access time C 2.7v to 3.6v: 90ns C 2.7v to 3.6v: 100ns n programming time: C 10s typical C double word programming option n program/erase controller (p/e.c.) n common flash interface C 64 bit security code n memory blocks C parameter blocks (top or bottom location) C main blocks n block protection on two parameter blocks Cwp for block protection n automatic stand-by mode n program and erase su spend n 100,000 program/erase cycles per block n 20 years of data retention C defectivity below 1ppm/year n electronic signature C manufacturer code: 20h C top device code, m28w160bt: 90h C bottom device code, m28w160bb: 91h figure 1. logic diagram ai02628 20 a0-a19 w dq0-dq15 v dd m28w160bt m28w160bb e v ss 16 g rp wp v ddq v pp tsop48 (n) 12 x 20mm bga46 (gb) 8 x 6 solder balls m bga
m28w160bt, m28w160bb 2/39 figure 2. bga connections (top view through package) ai02629 c b a 8 7 6 5 4 3 2 1 e d f a4 a7 v pp a8 a11 a13 a0 e dq8 dq5 dq14 a16 v ss dq0 dq9 dq3 dq6 dq15 v ddq dq1 dq10 v dd dq7 v ss dq2 a2 a5 a17 w a10 a14 a1 a3 a6 a9 a12 a15 rp a18 dq4 dq13 g dq12 dq11 wp a19 figure 3. tsop connections dq3 dq9 dq2 a6 dq0 w a3 nc dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15 v dd dq4 dq5 a7 dq7 v pp wp ai02630 m28w160bt m28w160bb 12 1 13 24 25 36 37 48 dq8 nc a19 a1 a18 a4 a5 dq1 dq11 g a12 a13 a16 a11 v ddq a15 a14 v ss e a0 rp v ss table 1. signal names a0-a19 address inputs dq0-dq7 data input/output, command inputs dq8-dq15 data input/output e chip enable g output enable w write enable rp reset wp write protect v dd supply voltage v ddq power supply for input/output buffers v pp optional supply voltage for fast program & erase v ss ground nc not connected internally 3/39 m28w160bt, m28w160bb description the m28w160b is a 16 mbit non-volatile flash memory that can be erased electrically at the block level and programmed in-system on a word-by- word basis. the device is offered in the tsop48 (10 x 20mm) and the bga46, 0.75mm ball pitch packages. when shipped, all bits of the m28w160b are in the 1 state. the array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. each block can be programmed and erased over 100,000 cycles. v ddq allows to drive the i/o pin down to 1.65v. an optional 12v v pp power supply is provided to speed up the program phase at customer production line environment. an internal command interface (c.i.) decodes the instructions to access/modify the memory content. the program/erase controller (p/e.c.) automati- cally executes the algorithms taking care of the timings necessary for program and erase opera- tions. verification is performed too, unburdening the microcontroller, while the status register tracks the status of the operation. the following instructions are executed by the m28w160b: read array, read electronic signa- ture, read status register, clear status register, program, double word program, block erase, program/erase suspend, program/erase re- sume and cfi query. organisation the m28w160b is organised as 1 mbit by 16 bits. a0-a19 are the address lines; dq0-dq15 are the data input/output. memory control is provided by chip enable e , output enable g and write enable w inputs. the program and erase operations are managed automatically by the p/e.c. block pro- tection against program or erase provides addi- tional data security. the upper two (or lower two) parameter blocks can be protected to secure the code content of the memory. wp controls protection and unprotection operations. memory blocks the device features an asymmetrical blocked ar- chitecture. the m28w160b has an array of 39 blocks: 8 parameter blocks of 4 kword and 31 main blocks of 32 kword. m28w160bt has the parameter blocks at the top of the memory ad- dress space while the m28w160bb locates the parameter blocks starting from the bottom. the memory maps are shown in tables 3 and 4. the two upper parameter block can be protected from accidental programming or erasure using wp . each block can be erased separately. erase can be suspended in order to perform either read or program in any other block and then resumed. program can be suspended to read data in any other block and then resumed. table 2. absolute maximum ratings (1) note: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other condition s above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. depends on range. symbol parameter value unit t a ambient operating temperature (2) C40 to 85 c t bias temperature under bias C40 to 125 c t stg storage temperature C55 to 155 c v io input or output voltage C0.6 to v ddq +0.6 v v dd , v ddq supply voltage C0.6 to 4.1 v v pp program voltage C0.6 to 13 v m28w160bt, m28w160bb 4/39 table 3. top boot block addresses, m28w160bt # size (kword) address range 38 4 ff000-fffff 37 4 fe000-fefff 36 4 fd000-fdfff 35 4 fc000-fcfff 34 4 fb000-fbfff 33 4 fa000-fafff 32 4 f9000-f9fff 31 4 f8000-f8fff 30 32 f0000-f7fff 29 32 e8000-effff 28 32 e0000-e7fff 27 32 d8000-dffff 26 32 d0000-d7fff 25 32 c8000-cffff 24 32 c0000-c7fff 23 32 b8000-bffff 22 32 b0000-b7fff 21 32 a8000-affff 20 32 a0000-a7fff 19 32 98000-9ffff 18 32 90000-97fff 17 32 88000-8ffff 16 32 80000-87fff 15 32 78000-7ffff 14 32 70000-77fff 13 32 68000-6ffff 12 32 60000-67fff 11 32 58000-5ffff 10 32 50000-57fff 9 32 48000-4ffff 8 32 40000-47fff 7 32 38000-3ffff 6 32 30000-37fff 5 32 28000-2ffff 4 32 20000-27fff 3 32 18000-1ffff 2 32 10000-17fff 1 32 08000-0ffff 0 32 00000-07fff table 4. bottom boot block addresses, m28w160bb # size (kword) address range 38 32 f8000-fffff 37 32 f0000-f7fff 36 32 e8000-effff 35 32 e0000-e7fff 34 32 d8000-dffff 33 32 d0000-d7fff 32 32 c8000-cffff 31 32 c0000-c7fff 30 32 b8000-bffff 29 32 b0000-b7fff 28 32 a8000-affff 27 32 a0000-a7fff 26 32 98000-9ffff 25 32 90000-97fff 24 32 88000-8ffff 23 32 80000-87fff 22 32 78000-7ffff 21 32 70000-77fff 20 32 68000-6ffff 19 32 60000-67fff 18 32 58000-5ffff 17 32 50000-57fff 16 32 48000-4ffff 15 32 40000-47fff 14 32 38000-3ffff 13 32 30000-37fff 12 32 28000-2ffff 11 32 20000-27fff 10 32 18000-1ffff 9 32 10000-17fff 8 32 08000-0ffff 7 4 07000-07fff 6 4 06000-06fff 5 4 05000-05fff 4 4 04000-04fff 3 4 03000-03fff 2 4 02000-02fff 1 4 01000-01fff 0 4 00000-00fff 5/39 m28w160bt, m28w160bb signal descriptions see figure 1 and table 1. address inputs (a0-a19). the address signals are inputs driven with cmos voltage levels. they are latched during a write operation. data input/output (dq0-dq15). the data in- puts, a word to be programmed or a command to the c.i., are latched on the chip enable e or write enable w rising edge, whichever occurs first. the data output from the memory array, the electronic signature or status register is valid when chip enable e and output enable g are active. the output is high impedance when the chip is dese- lected, the outputs are disabled or rp is tied to v il . commands are issued on dq0-dq7. chip enable (e ). the chip enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. e at v ih deselects the memory and reduces the power consumption to the stand-by level. e can also be used to control writing to the command register and to the memo- ry array, while w remains at v il . output enable (g ). the output enable controls the data input/output buffers. write enable (w ). this input controls writing to the command register, input address and data latches. write protect (wp ). write protect is an input to protect or unprotect the two lockable parameter blocks. when wp is at v il , the lockable blocks are protected. program or erase operations are not achievable. when wp is at v ih , the lockable blocks are unprotected and they can be pro- grammed or erased (refer to table 9). reset input (rp ). the rp input provides hard- ware reset of the memory. when rp is at v il , the memory is in reset mode: the outputs are put to high-z and the current consumption is minimised. when rp is at v ih , the device is in normal opera- tion. exiting reset mode the device enters read ar- ray mode. v dd supply voltage (2.7v to 3.6v). v dd pro- vides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). it ranges from 2.7v to 3.6v. v ddq supply voltage (1.65v to v dd ). v ddq provides the power supply to the i/o pins and en- ables all outputs to be powered independently from v dd . v ddq can be tied to v dd or it can use a separate supply. it can be powered either from 1.65v to 2.2v or from 2.7v to 3.6v. v pp program supply voltage (12v). v pp is both a control input and a power supply pin. the two functions are selected by the voltage range applied to the pin. if v pp is kept in a low voltage range (0v to 3.6v) v pp is seen as a control input. in this case a volt- age lower than v pplk gives an absolute protection against program or erase, while v pp > v pp1 en- ables these functions. v pp value is only sampled at the beginning of a program or erase; a change in its value after the operation has been started does not have any effect and program or erase are carried on regularly. if v pp is used in the range 11.4v to 12.6v acts as a power supply pin. in this condition v pp value must be stable until p/e algorithm is completed (see table 22 and 23). v ss ground. v ss is the reference for all the volt- age measurements. m28w160bt, m28w160bb 6/39 device operations four control pins rule the hardware access to the flash memory: e , g , w , rp . the following opera- tions can be performed using the appropriate bus cycles: read, write the command of an instruc- tion, output disable, stand-by, reset (see table 5). read. read operations are used to output the contents of the memory array, the electronic sig- nature, the status register and the cfi. both chip enable (e ) and output enable (g ) must be at v il in order to perform the read operation. the chip enable input should be used to enable the device. output enable should be used to gate data onto the output independently of the device selection. the data read depend on the previous command written to the memory (see instructions rd, rsig, rsr, rcfi). read array is the default state of the device when exiting reset or after power-up. write. write operations are used to give com- mands to the memory or to latch input data to be programmed. a write operation is initiated when chip enable e and write enable w are at v il with output enable g at v ih . commands, input data and addresses are latched on the rising edge of w or e , whichever occur first. output disable. the data outputs are high im- pedance when the output enable g is at v ih . stand-by. stand-by disables most of the internal circuitry allowing a substantial reduction of the cur- rent consumption. the memory is in stand-by when chip enable e is at v ih and the device is in read mode. the power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the output enable g or write enable w inputs. if e switches to v ih during program or erase operation, the device en- ters in stand-by when finished. reset. during reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high impedance. the memory is in reset mode when rp is at v il . the power con- sumption is reduced to the stand-by level, inde- pendently from the chip enable e , output enable g or write enable w inputs. if rp is pulled to v ss during a program or erase, this operation is abort- ed and the memory content is no longer valid as it has been compromised by the aborted operation. table 5. user bus operations (1) note: 1. x = v il or v ih , v pph = 12v 5%. table 6. read electronic signature (rsig instruction) note: 1. rp = v ih . operation e g w rp wp v pp dq0-dq15 read v il v il v ih v ih x don't care data output write v il v ih v il v ih x v dd or v pph data input output disable v il v ih v ih v ih x don't care hi-z stand-by v ih xx v ih x don't care hi-z reset x x x v il x don't care hi-z code device e g w a0 a1-a7 a8-a19 dq0-dq7 dq8-dq15 manufact. code v il v il v ih v il v il don't care 20h 00h device code m28w160bt v il v il v ih v ih v il don't care 90h 00h m28w160bb v il v il v ih v ih v il don't care 91h 00h 7/39 m28w160bt, m28w160bb instructions and commands eleven instructions are available (see tables 7 and 8) to perform read memory array, read sta- tus register, read electronic signature, cfi que- ry, erase, program, double word program, clear status register, program/erase suspend and program/erase resume. status register output may be read at any time, during programming or erase, to monitor the progress of the operation. an internal command interface (c.i.) decodes the instructions while an internal program/erase con- troller (p/e.c.) handles all timing and verifies the correct execution of the program and erase in- structions. p/e.c. provides a status register whose bits indicate operation and exit status of the internal algorithms. the command interface is reset to read array when power is first applied, when exiting from re- set or whenever v dd is lower than v lko . com- mand sequence must be followed exactly. any invalid combination of commands will reset the de- vice to read array. read (rd) the read instruction consists of one write cycle (refer to device operations section) giving the command ffh. next read operations will read the addressed location and output the data. when a device reset occurs, the memory is in read array as default. read status register (rsr) the status register indicates when a program or erase operation is complete and the success or failure of operation itself. issue a read status register instruction (70h) to read the status reg- ister content. the read status register instruction may be is- sued at any time, also when a program/erase op- eration is ongoing. the following read operations output the content of the status register. the sta- tus register is latched on the falling edge of e or g signals, and can be read until e or g returns to v ih . either e or g must be toggled to update the latched data. additionally, any read attempt during program or erase operation will automatically out- put the content of the status register. read electronic signature (rsig) the read electronic signature instruction con- sists of one write cycle (refer to device operations section) giving the command 90h. a subsequent read will output the manufacturer or the device code (electronic signature) depending on the lev- els of a0 (see tables 6). the electronic signature can be read from the memory allowing program- ming equipment or applications to automatically match their interface to the characteristics of m28w160b. the manufacturer code is output when the address lines a0 is at v il , the device code is output when a0 is at v ih . address a1-a7 must be kept to v il , other addresses are ignored. the codes are output on dq0-dq7 with dq8- dq15 at 00h. cfi query (rcfi) the common flash interface query mode is en- tered by writing 98h. next read operations will read the cfi data. the cfi data structure contains also a security area; in this section, a 64 bit unique se- curity number is written, starting at address 80h. this area can be accessed only in read mode by the final use and there are no ways of changing the code after it has been written by st. write a read instruction to return to read mode (refer to the common flash interface section). table 7. commands hex code command 00h, 01h, 60h, 2fh, c0h invalid/reserved 10h alternative program set-up 20h erase set-up 30h double word program set-up 40h program set-up 50h clear status register 70h read status register 90h or 98h read electronic signature, or cfi query b0h program/erase suspend d0h program/erase resume, or erase confirm ffh read array m28w160bt, m28w160bb 8/39 status register bit b7 returns 0 while the erasure is in progress and 1 when it has completed. after completion the status register bit b5 returns 1 if there has been an erase failure. status register bit b1 returns 1 if the user is attempting to pro- gram a protected block. status register bit b3 re- turns a 1 if v pp is below v pplk . erase aborts if rp turns to v il . as data integrity cannot be guaranteed when the erase operation is aborted, the erase must be repeated. a clear sta- tus register instruction must be issued to reset b1, b3, b4 and b5 of the status register. during the execution of the erase by the p/e.c., the memory accepts only the rsr (read status register) and pes (program/erase suspend) instructions. table 8. instructions note: 1. x = don't care. 2. the first cycle of the rd, rsr, rsig or rcfi instruction is followed by read operations to read memory array, status register or electronic signature codes. any number of read cycle can occur after one command cycle. 3. signature address bit a0=v il will output manufacturer code. address bit a0=v ih will output device code. address a7-a1 must be kept to v il . other address bits are ignored. 4. address 1 and address 2 must be consecutive addresses differing only for address bit a0. mne- monic instruction cycles 1st cycle 2nd cycle 3nd cycle operat. addr. (1) data operat. addr. data operat. addr. data rd read memory array 1+ write x ffh read (2) read address data rsr read status register 1+ write x 70h read (2) x status register rsig read electronic signature 1+ write x 90h or 98h read (2) signature address (3) signature rcfi cfi query 1+ write 55h 98h or 90h read (2) cfi address query ee erase 2 write x 20h write block address d0h pg program 2 write x 40h or 10h write address data input dpg (4) double word program 3 write x 30h write address 1 data input write address 2 data input clrs clear status register 1write x 50h pes program/ erase suspend 1write x b0h per program/ erase resume 1write x d0h erase (ee) block erasure sets all the bits within the selected block to 1. one block at a time can be erased. it is not necessary to program the block with 00h as the p/e.c. will do it automatically before erasing. this instruction uses two write cycles. the first command written is the erase set up command 20h. the second command is the erase confirm command d0h. an address within the block to be erased is given and latched into the memory dur- ing the input of the second command. if the sec- ond command given is not an erase confirm, the status register bits b4 and b5 are set and the in- struction aborts. read operations output the status register after erasure has started. 9/39 m28w160bt, m28w160bb table 9. memory blocks protection truth table note: 1. notes:1.x' = don't care 2. rp is the reset/power down. 3. v pp is the program or erase supply voltage. 4. v ih /v il are logic high and low levels. 5. v pp must be also greater than the program voltage lock-out v pplk . table 10. status register bits note: logic level '1' is high, '0' is low. v pp (1,3) rp (2,4) wp (1,4) lockable blocks other blocks x v il x protected protected v il v ih x protected protected v dd or v pph (5) v ih v il protected unprotected v dd or v pph (5) v ih v ih unprotected unprotected mnemonic bit name logic level definition note p/ecs 7 p/e.c. status '1' ready indicates the p/e.c. status, check during program or erase, and on completion before checking bits b4 or b5 for program or erase success '0' busy ess 6 erase suspend status '1' suspended on an erase suspend instruction p/ecs and ess bits are set to '1'. ess bit remains '1' until an erase resume instruction is given. '0' in progress or completed es 5 erase status '1' erase error es bit is set to '1' if p/e.c. has applied the maximum number of erase pulses to the block without achieving an erase verify. '0' erase success ps 4 program status '1' program error ps bit set to '1' if the p/e.c. has failed to program a word. '0' program success vpps 3 v pp status '1' v pp invalid, abort vpps bit is set if the v pp voltage is below v pplk when a program or erase instruction is executed. v pp is sampled only at the beginning of the erase/program operation. '0' v pp ok pss 2 program suspend status '1' suspended on a program suspend instruction p/ecs and pss bits are set to '1'. pss remains '1' until a program resume instruction is given '0' in progress or completed bps 1 block protection status '1' program/erase on protected block, abort bps bit is set to '1' if a program or erase operation has been attempted on a protected block '0' no operation to protected blocks 0 reserved m28w160bt, m28w160bb 10/39 program (pg) the memory array can be programmed word-by- word. this instruction uses two write cycles. the first command written is the program set-up com- mand 40h (or 10h). a second write operation latch- es the address and the data to be written and starts the p/e.c. read operations output the status register con- tent after the programming has started. the status register bit b7 returns 0 while the programming is in progress and 1 when it has completed. after completion the status register bit b4 returns 1 if there has been a program failure. status register bit b1 returns 1 if the user is attempting to pro- gram a protected block. status register bit b3 re- turns a 1 if v pp is below v pplk . programming aborts if rp goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and reprogrammed. a clear status register instruc- tion must be issued to reset b4, b3 and b1 of the status register. during the execution of the program by the p/e.c., the memory accepts only the rsr (read status register) and pes (program/erase suspend) in- structions. double word program (dpg) this feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.the two words must differ only for the address a0. programming should not be attempt- ed when v pp is not at v pph . the operation can also be executed if v pp is below v pph but result could be uncertain. this instruction uses three write cycles. the first command written is the dou- ble word program set-up command 30h. a sec- ond write operation latches the address and the data of the first word to be written, the third write operation latches the address and the data of the second word to be written and starts the p/e.c. read operations output the status register con- tent after the programming has started. the status register bit b7 returns 0 while the programming is in progress and 1 when it has completed. after completion the status register bit b4 returns 1 if there has been a program failure. status register bit b1 returns 1 if the user is attempting to pro- gram a protected block. status register bit b3 re- turns a 1 if v pp is below v pplk . programming aborts if rp goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and reprogrammed. a clear status register instruc- tion must be issued to reset b4, b3 and b1 of the status register. during the execution of the program by the p/e.c., the memory accepts only the rsr (read status register) and pes (program/erase suspend) in- structions. clear status register (clrs) the clear status register uses a single write op- eration which clears bits b1, b3, b4 and b5 to 0. its use is necessary before any new operation when an error has been detected. the clear status register is executed writing the command 50h. program/erase suspend (pes) program/erase suspend is accepted only during the program erase instruction execution. when a program/erase suspend command is written to the c.i., the p/e.c. freezes the program/erase op- eration. program/erase resume (per) continues the program/erase operation. program/erase suspend consists of writing the command b0h without any specific address. the status register bit b2 is set to 1 (within 5s) when the program has been suspended. b2 is set to 0 in case the program is completed or in progress. the status register bit b6 is set to 1 (within 30s) when the erase has been suspend- ed. b6 is set to 0 in case the erase is completed or in progress. the valid commands while erase is suspended are program/erase resume, pro- gram, read array, read status register, read identifier, cfi query. while program is suspended the same command set is valid except for program instruction. during program/erase suspend mode, the chip can be placed in a pseudo-stand-by mode by taking e to v ih . this reduces active current con- sumption. program/erase is aborted if rp turns to v il . program/erase resume (per) if a program/erase suspend instruction was previ- ously executed, the program/erase operation may be resumed by issuing the command d0h. the status register bit b2/b6 is cleared when program/ erase resumes. read operations output the status register after the program/erase is resumed. the suggested flow charts for programs that use the programming, erasure and program/erase suspend/resume features of the memories are shown from figures 10, 11, 12, 13 and 14. 11/39 m28w160bt, m28w160bb table 11. program, erase times and program/erase endurance cycles (t a = 0 to 70c or C40 to 85c; v dd = 2.7v to 3.6v) note: t a = 25 c. parameter test conditions m28w160b unit min typ (1) max word program v pp = v dd 10 200 s double word program v pp = 12v 5% 10 200 s main block program v pp = 12v 5% 0.16 5 sec v pp = v dd 0.32 5 sec parameter block program v pp = 12v 5% 0.02 4 sec v pp = v dd 0.04 4 sec main block erase v pp = 12v 5% 110 sec v pp = v dd 110 sec parameter block erase v pp = 12v 5% 0.8 10 sec v pp = v dd 0.8 10 sec program/erase cycles (per block) 100,000 cycles m28w160bt, m28w160bb 12/39 block protection two parameter blocks (#0 and #1) can be protect- ed against program or erase to ensure extra data security. unprotected blocks can be programmed or erased. wp tied to v il protects the two lockable blocks. v pp below v pplk protects all the blocks. any pro- gram or erase operation on protected blocks is aborted. the status register tracks when the event occurs. table 9 defines the protection methods. power consumption the m28w160b puts itself in one of four different modes depending on the status of the control sig- nals: active power, automatic stand-by, stand-by and reset define decreasing levels of current con- sumption. these allow the memory power to be minimised, in turn decreasing the overall system power consumption. as different recovery time are linked to the different modes, please refer to the ac timing table to design your system. active power when e is at v il and rp is at v ih , the device is in active mode. refer to dc characteristics to get the values of the current supply consumption. automatic stand-by automatic stand-by provides a low power con- sumption state during read mode. following a read operation, after a delay close to the memory access time, the device enters automatic stand- by: the supply current is reduced to i cc1 values. the device keeps the last output data stable, till a new location is accessed. stand-by or reset refer to the device operations section. power up the supply voltage v dd and the program supply voltage v pp can be applied in any order. the memory command interface is reset on power up to read memory array, but a negative transition of chip enable e or a change of the addresses is re- quired to ensure valid data outputs. care must be taken to avoid writes to the memory when v dd is above v lko . writes can be inhibited by driving ei- ther e or w to v ih . the memory is disabled if rp is at v il . supply rails normal precautions must be taken for supply volt- age decoupling, each device in a system should have the v dd and v pp rails decoupled with a 0.1f capacitor close to the v dd and v pp pins. the pcb trace widths should be sufficient to carry the required v pp program and erase currents. 13/39 m28w160bt, m28w160bb common flash interface (cfi) the common flash interface (cfi) specification is a jedec approved, standardised data structure that can be read from the flash memory device. cfi allows a system software to query the flash device to determine various electrical and timing parameters, density information and functions supported by the device. cfi allows the system to easily interface to the flash memory, to learn about its features and parameters, enabling the software to configure itself when necessary. tables 12, 13, 14, 15, 16 and 17 show the address used to retrieve each data. the cfi data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. tables 12, 13, 14 and 15 show the addresses used to retrieve each data. the cfi data structure contains also a security area; in this section, a 64 bit unique secu- rity number is written, starting at address 80h. this area can be accessed only in read mode by the fi- nal user and there are no ways of changing the code after it has been written by st. write a read instruction to return to read mode. refer to the cfi query instruction to understand how the m28w160b enters the cfi query mode. table 12. query structure overview note: the flash memory display the cfi data structure when cfi query command is issued. in this table are listed the main sub-se ctions detailed in tables 13, 14, 15, 16 and 17. query data are always presented on the lowest order data outputs. table 13. cfi query identification string note: query data are always presented on the lowest - order data outputs (dq7-dq0) only. dq8-dq15 are 0. offset sub-section name description 00h reserved reserved for algorithm-specific information 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) offset data description 00h 0020h manufacturer code 01h 0090h - top 0091h - bottom device code 02h-0fh reserved reserved 10h 0051h query unique ascii string "qry" 11h 0052h query unique ascii string "qry" 12h 0059h query unique ascii string "qry" 13h 0003h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 14h 0000h 15h offset = p = 0035h address for primary algorithm extended query table 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported (note: 0000h means none exists) 18h 0000h 19h value = a = 0000h address for alternate algorithm extended query table note: 0000h means none exists 1ah 0000h m28w160bt, m28w160bb 14/39 table 14. cfi query system interface information offset data description 1bh 0027h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 1ch 0036h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 1dh 00b4h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv note: this value must be 0000h if no v pp pin is present 1eh 00c6h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv note: this value must be 0000h if no v pp pin is present 1fh 0004h typical timeout per single byte/word program (multi-byte program count = 1), 2 n s (if supported; 0000h = not supported) 20h 0000h typical timeout for maximum-size multi-byte program or page write, 2 n s (if supported; 0000h = not supported) 21h 000ah typical timeout per individual block erase, 2 n ms (if supported; 0000h = not supported) 22h 0000h typical timeout for full chip erase, 2 n ms (if supported; 0000h = not supported) 23h 0004h maximum timeout for byte/word program, 2 n times typical (offset 1fh) (0000h = not supported) 24h 0000h maximum timeout for multi-byte program or page write, 2 n times typical (offset 20h) (0000h = not supported) 25h 0003h maximum timeout per individual block erase, 2 n times typical (offset 21h) (0000h = not supported) 26h 0000h maximum timeout for chip erase, 2 n times typical (offset 22h) (0000h = not supported) 15/39 m28w160bt, m28w160bb table 15. device geometry definition offset word mode data description 27h 0015h device size = 2 n in number of bytes 28h 0001h flash device interface code description: asynchronous x16 29h 0000h 2ah 0000h maximum number of bytes in multi-byte program or page = 2 n 2bh 0000h 2ch 0002h number of erase block regions within device bit 7 to 0 = x = number of erase block regions note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk." 2. x specifies the number of regions within the device containing one or more con- tiguous erase blocks of the same size. for example, a 128kb device (1mb) having blocking of 16kb, 8kb, four 2kb, two 16kb, and one 64kb is consid- ered to have 5 erase block regions. even though two regions both contain 16kb blocks, the fact that they are not contiguous means they are separate erase block regions. 3. by definition, symmetrically block devices have only one blocking region. m28w160bt m28w160bt erase block region information bit 31 to 16 = z, where the erase block(s) within this region are (z) times 256 bytes in size. the value z = 0 is used for 128 byte block size. e.g. for 64kb block size, z = 0100h = 256 => 256 * 256 = 64k bit 15 to 0 = y, where y+1 = number of erase blocks of identical size within the erase block region: e.g. y = d15-d0 = ffffh => y+1 = 64k blocks [maximum number] y = 0 means no blocking (# blocks = y+1 = "1 block") note: y = 0 value must be used with number of block regions of one as indicated by (x) = 0 2dh 001eh 2eh 0000h 2fh 0000h 30h 0001h 31h 0007h 32h 0000h 33h 0020h 34h 0000h m28w160bb m28w160bb 2dh 0007h 2eh 0000h 2fh 0020h 30h 0000h 31h 001eh 32h 0000h 33h 0000h 34h 0001h m28w160bt, m28w160bb 16/39 table 16. primary algorithm-specific extended query table table 17. security code area offset data description (p)h = 35h 0050h primary algorithm extended query table unique ascii string pri 0052h 0049h (p+3)h = 38h 0031h major version number, ascii (p+4)h = 39h 0030h minor version number, ascii (p+5)h = 3ah 0006h extended query table contents for primary algorithm bit 0 chip erase supported (1 = yes, 0 = no) bit 1 erase suspend supported (1 = yes, 0 = no) bit 2 program suspend (1 = yes, 0 = no) bit 3 lock/unlock supported (1 = yes, 0 = no) bit 4 quequed erase supported (1 = yes, 0 = no) bit 31 to 5 reserved; undefined bits are 0 0000h (p+7)h 0000h (p+8)h 0000h (p+9)h = 3eh 0001h supported functions after suspend read array, read status register and cfi query are always supported during erase or program operation bit 0 program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1 reserved; undefined bits are 0 (p+a)h = 3fh 0000h block lock status defines which bits in the block status register section of the query are implemented. bit 0 block lock status register lock/unlock bit active (1 = yes, 0 = no) bit 1 block lock status register lock-down bit active (1 = yes, 0 = no) bit 15 to 2 reserved for future use; undefined bits are 0 (p+b)h 0000h (p+c)h = 41h 0027h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv (p+d)h = 42h 00c0h v pp supply optimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv (p+e)h 0000h reserved offset data description 81h xxxx 64 bits unique device number. 82h xxxx 83h xxxx 84h xxxx 17/39 m28w160bt, m28w160bb table 18. dc characteristics (t a = 0 to 70c or C40 to 85c; v dd = v ddq = 2.7v to 3.6v) symbol parameter test condition min typ max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 10 a i cc supply current (read) e = v ss , g = v ih , f = 5mhz 10 20 ma i cc1 supply current (stand-by or automatic stand-by) e = v ddq 0.2v, rp = v ddq 0.2v 15 50 a i cc2 supply current (reset) rp = v ss 0.2v 15 50 a i cc3 supply current (program) program in progress v pp = 12v 5% 10 20 ma program in progress v pp = v dd 10 20 ma i cc4 supply current (erase) erase in progress v pp = 12v 5% 520ma erase in progress v pp = v dd 520ma i cc5 supply current (program/erase suspend) e = v ddq 0.2v, erase suspended 50 a i pp program current (read or stand-by) v pp > v dd 400 a i pp1 program current (read or stand-by) v pp v dd 5a i pp2 program current (reset) rp = v ss 0.2v 5a i pp3 program current (program) program in progress v pp = 12v 5% 10 ma program in progress v pp = v dd 5a i pp4 program current (erase) erase in progress v pp = 12v 5% 10 ma erase in progress v pp = v dd 5a v il input low voltage C0.5 0.4 v v ddq 3 2.7v C0.5 0.8 v v ih input high voltage v ddq C0.4 v ddq +0.4 v v ddq 3 2.7v 0.7 v ddq v ddq +0.4 v v ol output low voltage i ol = 100a, v dd = v dd min, v ddq = v ddq min 0.1 v v oh output high voltage i oh = C100a, v dd = v dd min, v ddq = v ddq min v ddq C0.1 v v pp1 program voltage (program or erase operations) 1.65 3.6 v v pph program voltage (program or erase operations) 11.4 12.6 v v pplk program voltage (program and erase lock-out) 1v v lko v dd supply voltage (program and erase lock-out) 2v m28w160bt, m28w160bb 18/39 figure 5. ac testing load circuit ai00609b v ddq /2 out c l = 50pf c l includes jig capacitance 3.3k w 1n914 device under test table 19. ac measurement conditions input rise and fall times 10ns input pulse voltages 0 to v ddq input and output timing ref. voltages v ddq /2 figure 4. ac testing input output waveform ai00610 v ddq 0v v ddq /2 table 20. capacitance (1) (t a = 25 c, f = 1 mhz) note: 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v 6pf c out output capacitance v out = 0v 12 pf 19/39 m28w160bt, m28w160bb table 21. read ac characteristics (1) ( t a = 0 to 70c or C40 to 85c) note: 1. see ac testing measurement conditions for timing measurements. 2. sampled only, not 100% tested. 3. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . 4. the device reset is possible but not guaranteed if t plph < 100ns. symbol alt parameter m28w160b unit 90 100 v dd = 2.7v to 3.6v v ddq = 2.7v min v dd = 2.7v to 3.6v v ddq = 1.65v min min max min max t avav t rc address valid to next address valid 90 100 ns t av qv t acc address valid to output valid 90 100 ns t axqx (2) t oh address transition to output transition 0 0 ns t ehqx (2) t oh chip enable high to output transition 0 0 ns t ehqz (2) t hz chip enable high to output hi-z 25 30 ns t elqv (3) t ce chip enable low to output valid 90 100 ns t elqx (2) t lz chip enable low to output transition 0 0 ns t ghqx (2) t oh output enable high to output transition 0 0 ns t ghqz (2) t df output enable high to output hi-z 25 30 ns t glqv (3) t oe output enable low to output valid 30 35 ns t glqx (2) t olz output enable low to output transition 0 0 ns t phqv t pwh reset high to output valid 150 150 ns t plph (2,4) t rp reset pulse width 100 100 ns m28w160bt, m28w160bb 20/39 figure 6. read ac waveforms dq0-dq15 ai00619 valid a0-a19 e rp taxqx tavav valid tavqv telqv telqx tglqv tglqx tphqv power-up and standby address valid and chip enable outputs enabled data valid standby g tghqx tghqz tehqx tehqz note: write enable (w ) = high. 21/39 m28w160bt, m28w160bb table 22. write ac characteristics, write enable controlled (1) (t a = 0 to 70c or C40 to 85c) note: 1. see ac testing measurement conditions for timing measurements. 2. sampled only, not 100% tested. 3. the device reset is possible but not guaranteed if t plph < 100ns. 4. the reset will complete within 100ns if rp is asserted while not in program nor in erase mode. 5. applicable if v pp is seen as a logic input (v pp < 3.6v). symbol alt parameter m28w160b unit 90 100 v dd = 2.7v to 3.6v v ddq = 2.7v min v dd = 2.7v to 3.6v v ddq = 1.65v min min max min max t avav t wc write cycle time 90 100 ns t avwh t as address valid to write enable high 50 50 ns t dvwh t ds data valid to write enable high 50 50 ns t elwl t cs chip enable low to write enable low 0 0 ns t phwl t ps reset high to write enable low 90 100 ns t plph (2, 3) t rp reset pulse width 100 100 ns t plrh (2, 4) reset low to program/erase abort 30 30 s t qvvpl (2, 5) output valid to v pp low 00ns t qvwpl data valid to write protect low 0 0 ns t vphwh (2) t vps v pp high to write enable high 200 200 ns t whax t ah write enable high to address transition 0 0 ns t whdx t dh write enable high to data transition 0 0 ns t wheh t ch write enable high to chip enable high 0 0 ns t whgl write enable high to output enable low 30 30 ns t whwl t wph write enable high to write enable low 30 30 ns t wlwh t wp write enable low to write enable high 50 50 ns t wphwh write protect high to write enable high 50 50 ns m28w160bt, m28w160bb 22/39 figure 7. write ac waveforms, w controlled e g w dq0-dq15 command cmd or data status register rp v pp valid a0-a19 tavav tqvvpl tavwh twhax program or erase telwl twheh twhdx tdvwh twlwh tphwl twhwl tvphwh power-up and set-up command confirm command or data input status register read 1st polling twhqv ai03572 twphwh wp twhgl tqvwpl 23/39 m28w160bt, m28w160bb table 23. write ac characteristics, chip enable controlled (1) (t a = 0 to 70c or C40 to 85c) note: 1. see ac testing measurement conditions for timing measurements. 2. sampled only, not 100% tested. 3. the device reset is possible but not guaranteed if t plph < 100ns. 4. the reset will complete within 100ns if rp is asserted while not in program nor in erase mode. 5. applicable if v pp is seen as a logic input (v pp < 3.6v). symbol alt parameter m28w160b unit 90 100 v dd = 2.7v to 3.6v v ddq = 2.7v min v dd = 2.7v to 3.6v vddq = 1.65v min min max min max t avav t wc write cycle time 90 100 ns t av eh t as address valid to chip enable high 50 50 ns t dveh t ds data valid to chip enable high 50 50 ns t ehax t ah chip enable high to address transition 0 0 ns t ehdx t dh chip enable high to data transition 0 0 ns t ehel t cph chip enable high to chip enable low 30 30 ns t ehgl chip enable high to output enable low 30 30 ns t ehwh t wh chip enable high to write enable high 0 0 ns t eleh t cp chip enable low to chip enable high 50 50 ns t phel t ps reset high to chip enable low 90 100 ns t plph (2, 3) t rp reset pulse width 100 100 ns t plrh (2, 4) reset low to program/erase abort 30 30 s t qvvpl (2, 5) output valid to v pp low 00ns t qvwpl data valid to write protect low 0 0 ns t vpheh (2) t vps v pp high to chip enable high 200 200 ns t wlel t cs write enable low to chip enable low 0 0 ns t wpheh write protect high to chip enable high 50 50 ns m28w160bt, m28w160bb 24/39 figure 8. write ac waveforms, e controlled e g dq0-dq15 command cmd or data status register rp v pp valid a0-a19 tavav tqvvpl taveh tehax program or erase twlel tehwh tehdx tdveh teleh tphel tehel tvpheh power-up and set-up command confirm command or data input status register read 1st polling tehqv ai03573 w twpheh wp tehgl tqvwpl 25/39 m28w160bt, m28w160bb figure 9. reset ac waveform ai03537 tphqv rp tplph rp tplph reset during read mode reset during program with t plph t plrh tplrh tphwl tphel abort complete rp tplph reset during program/erase with t plph > t plrh tplrh tphwl tphel abort complete reset m28w160bt, m28w160bb 26/39 figure 10. program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) can be made after each program operationor after a sequence. 2. if an error is found, the status register must be cleared (clrs instruction) before further p/e.c. operations. write 40h or 10h command ai03538 start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) program instruction: C write 40h or 10h command C write address & data (memory enters read status state after the program instruction) do: C read status register (e or g must be toggled) if pes instruction given execute suspend program loop while b7 = 1 if b3 = 1, v pp invalid error: C error handler if b4 = 1, program error: C error handler yes end yes no b1 = 0 program to protected block error (1, 2) if b1 = 1, program to protected block error: C error handler suspend suspend loop no yes 27/39 m28w160bt, m28w160bb figure 11. double word program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared (clrs instruction) before further p/e.c. operations. 3. address 1 and address 2 must be consecutive addresses differing only for bit a0. write 30h command ai03539 start write address 1 & data 1 (3) read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) dpg instruction: C write 30h command C write address 1 & data 1 (3) C write address 2 & data 2 (3) (memory enters read status state after the program instruction) do: C read status register (e or g must be toggled) if pes instruction given execute dpg suspend loop while b7 = 1 if b3 = 1, v pp invalid error: C error handler if b4 = 1, program error: C error handler yes end yes no b1 = 0 program to protected block error (1, 2) if b1 = 1, program to protected block error: C error handler suspend suspend loop no yes write address 2 & data 2 (3) m28w160bt, m28w160bb 28/39 figure 12. program or dpg suspend & resume flowchart and pseudo code write 70h command ai03540 read status register yes no b7 = 1 yes no b2 = 1 program continues write a read command pes instruction: C write b0h command do: C read status register (e or g must be toggled) while b7 = 1 if b2 = 0 program completed write d0h command per instruction: C write d0h command to resume the program C if the program operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend was not issued). read data from another address start write b0h command program complete write ffh command read data 29/39 m28w160bt, m28w160bb figure 13. erase flowchart and pseudo code note: 1. if an error is found, the status register must be cleared (clrs instruction) before further p/e.c. operations. write 20h command ai03541 start write block address & d0h command read status register yes no b7 = 1 yes no b3 = 0 no b4, b5 = 0 v pp invalid error (1) command sequence error (1) ee instruction: C write 20h command C write block address (a12-a20) & command d0h (memory enters read status state after the ee instruction) do: C read status register (e or g must be toggled) if pes instruction given execute suspend erase loop while b7 = 1 if b3 = 1, v pp invalid error: C error handler if b4, b5 = 1, command sequence error: C error handler yes no b5 = 0 erase error (1) yes no suspend suspend loop if b5 = 1, erase error: C error handler end yes no b1 = 0 erase to protected block error (1) if b1 = 1, erase to protected block error: C error handler yes m28w160bt, m28w160bb 30/39 figure 14. erase suspend & resume flowchart and pseudo code write 70h command ai03549 read status register yes no b7 = 1 yes no b6 = 1 erase continues pes instruction: C write b0h command do: C read status register (e or g must be toggled) while b7 = 1 if b6 = 0, erase completed write d0h command read data from another block or program start write b0h command erase complete write ffh command read data per instruction: C write d0h command to resume erasure C if the erase operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend was not issued). 31/39 m28w160bt, m28w160bb figure 15. command interface and program erase controller flowchart (a) note: 1. if no command is written, the command interface remains in its previous valid state. upon power-up, on exit from power-d own or if v dd falls below v lko , the command interface defaults to read array mode. 2. p/e.c. status (ready or busy) is read on status register bit 7. ai03547 read signature yes no 90h read status yes 70h no clear status yes 50h no program set-up yes 40h or 10h no erase set-up yes 20h no erase command error yes ffh wait for command write (1) read status read array yes d0h no a b no c cfi query yes 98h no dpg set-up yes 30h no c m28w160bt, m28w160bb 32/39 figure 16. command interface and program erase controller flowchart (b) note: 2. p/e.c. status (ready or busy) is read on status register bit 7. read status yes no 70h b erase yes ready (2) no a b0h no read status yes ready (2) no erase suspend yes d0h read array yes erase suspended read status (read status) yes no (read status) no erase resume 90h no read signature yes 98h no cfi query yes 30h no dpg set-up yes c no 40h or 10h program set-up yes c ai03548 33/39 m28w160bt, m28w160bb figure 17. command interface and program erase controller flowchart (c) note: 2. p/e.c. status (ready or busy) is read on status register bit 7. read status yes no 70h b program yes ready (2) no c b0h no read status yes ready (2) no program suspend yes d0h read array yes program suspended read status (read status) yes no (read status) no program resume 90h no read signature yes 98h no cfi query yes ai03545 m28w160bt, m28w160bb 34/39 table 24. ordering information scheme devices are shipped from the factory with the memory content bits erased to 1. table 25. daisy chain ordering scheme for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the stmicroelectronics sales office nearest to you. example: m28w160bt 90 n 6 t device type m28 operating voltage w = v dd = 2.7v to 3.6v; v ddq = 1.65v or 2.7v device function 160b = 16 mbit (1mb x16), boot block array matrix t = top boot b = bottom boot random speed 90 = 90 ns 100 = 100 ns package n = tsop48: 12 x 20 mm gb = bga46: 0.75 mm pitch temperature range 1 = 0 to 70 c 6 = C40 to 85 c option t = tape & reel packing example: m28w160b -gb t device type m28w160b daisy chain -gb = bga46: 0.75 mm pitch option t = tape & reel packing 35/39 m28w160bt, m28w160bb table 26. revision history date revision details july 1999 first issue 09/21/99 parameter block erase typ. specification change (table 11) added t whgl and t ehgl (tables 22, 23 and figures 7, 8) 10/20/99 bga package mechanical data change (table 27) daisy chain diagrams, package and pcb connections, added (figures 20, 21) 02/09/00 access time conditions change reset mode function change to remove power down mode instructions description clarification change of parameter block erase value (table 11) block protections description clarification security code area definition change (table 17) i cc2 and i cc3 value change (table 18) t plrh value change (tables 22, 23) program, erase, command interface flowcharts clarification (figures 10, 11, 12, 13, 14, 15, 16, 17) bga package mechanical data change (table 28) bga package outline diagram change (figure 19) 04/19/00 document type: from preliminary data to data sheet daisy chain part numbering defined bga daisy chain diagrams, package and pcb connections re-designed (figure 20, 21) 05/17/00 bga package outline diagram change (figure 19) m28w160bt, m28w160bb 36/39 table 27. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data symb mm inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.17 0.27 0.0067 0.0106 c 0.10 0.21 0.0039 0.0083 d 19.80 20.20 0.7795 0.7953 d1 18.30 18.50 0.7205 0.7283 e 11.90 12.10 0.4685 0.4764 e 0.50 C C 0.0197 C C l 0.50 0.70 0.0197 0.0276 a 0 5 0 5 n48 48 cp 0.10 0.0039 figure 18. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline drawing is not to scale. tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a 37/39 m28w160bt, m28w160bb table 28. bga46 - 8 x 6 balls, 0.75 mm pitch, package mechanical data symbol mm inch typ min max typ min max a 1.000 0.0394 a1 0.180 0.0071 a2 0.700 C C 0.0276 C C b 0.350 0.300 0.400 0.0138 0.0118 0.0157 d 6.390 6.340 6.440 0.2516 0.2496 0.2535 d1 5.250 C C 0.2067 C C ddd 0.008 0.0003 e 0.750 C C 0.0295 C C e 6.370 6.320 6.420 0.2508 0.2488 0.2528 e1 3.750 C C 0.1476 C C fd 0.570 C C 0.0224 C C fe 1.310 C C 0.0516 C C sd 0.375 C C 0.0148 C C se 0.375 C C 0.0148 C C figure 19. bga46 - 8 x 6 balls, 0.75 mm pitch, bottom view package outline drawing is not to scale. e1 e d1 d b a2 a1 a bga-g05 ddd e e fe sd se ball "a1" fd m28w160bt, m28w160bb 38/39 figure 20. bga46 daisy chain - package connections (top view through package) figure 21. bga46 daisy chain - pcb connections (top view through package) ai03298 c b a 8 7 6 5 4 3 2 1 e d f ai3299 c b a 8 7 6 5 4 3 2 1 e d f start point end point 39/39 m28w160bt, m28w160bb information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics a 2000 stmicroelectronics - all rights reserved all other names are the property of their respective owners. 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